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| Partnered With: 
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| M3000/M3001 Package-Feature Comparison |
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| Processor Control |
| JTAG |
Y |
Y |
Y |
| IBOOT_N, RePgm_Pmem |
Y |
Y |
Y |
| FLASH vs RAM Speed |
Y |
Y |
Y |
| Reset_N, XTAL |
Y |
Y |
Y |
| Fail_n |
Y |
Y |
N |
Memory (Code Space)
|
| Pmem...Addr Lines, Data lines, we, oe |
Y |
Y |
N |
| Memory Embedded (If N, External Memory is Required) |
N |
N |
Y |
Communications
|
| SPI_USR (Configurable as Master or Slave) |
Y |
Y |
Y |
| SPI_Master (Master Only) |
Y |
Y |
Y |
| CAN |
Y |
Y |
Y |
| UART |
Y |
Y |
Y |
Timers
|
| Timer (Internal, 8-bit timer0, 16-bit timer1) |
Y |
Y |
Y |
| Timer (External, 8-bit timer0, 16-bit timer1) |
Y |
Y |
Y |
| |
T0clk, T1clk, Ipc0 (timer1 only) |
Y |
N |
N |
| |
ocA |
Y |
Y |
N |
| |
ocB |
Y |
N |
N |
Indexer Logic
|
| Encoder_In |
Y |
Y |
Y |
| STEP_IO, DIR_IO |
Y |
Y |
Y |
| CAPTURE_IN, TRIP_OUT |
Y |
Y |
Y |
| External Interrupts [0..1] |
Y |
Y |
Y |
I/O Ports/Memory (Extra Data Space)
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| 8 GPIO [0..7] |
Y |
Y |
Y |
| 4 GPIO [8..11]/DataMem_A [8..11] |
Y |
Y |
Y |
| 8 GPIO [12..19]/DataMem_AD [0..7] |
Y |
N |
Y |
| DataMem_[CEN, ALE, WEN, OEN] |
Y |
N |
Y |
Analog
|
| Op_AMP [_Out, _M, _P] |
Y |
Y |
Y |
| adc_in |
Y |
Y |
N |
| Mux_ad_da |
Y |
Y |
Y |
| dac_out |
Y |
Y |
N |
Motor Bridge Driver Stage
|
| PhA_[LH, LL, RH, RL, Fwd, Rev] |
Y |
Y |
Y |
| PhB_[LH, LL, RH, RL, Fwd, Rev] |
Y |
Y |
Y |
| BridgeEnabled |
Y |
Y |
Y |
| PhA_Pwm, PhB_Pwm |
Y |
Y |
N |
| Pwm_Osc, Mask, Sin_Sign |
Y |
N |
N |
| Zero_Cross_Out |
Y |
Y |
Y |
| Sin_Out, Cos_Out |
Y |
Y |
Y |
| Cur_Out |
Y |
Y |
Y |
| Pwm_Current_Reference_Out |
Y |
N |
N |
| dac_SDA, dac_CS_N |
Y |
N |
N |
| EN_Pin |
Y |
N |
N |
| Inv_HBC |
Y |
N |
N |
| Fault_IN_N |
Y |
Y |
Y |
| Inv_LBC |
Y |
Y |
Y |
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